Random Access Memory (RAM) is a type of short-term data storage that the computer processor can quickly access. It consists of an array of addressable storage cells that each stores a bit of information (either a zero or one).
RAM falls into two general categories, static and dynamic. The storage unit of a static RAM (SRAM) cell is typically a bi-stable flip-flop whose state indicates the stored value. The storage unit of a dynamic RAM (DRAM) cell is typically an integrated circuit capacitor whose charge indicates the stored value. Because the capacitor leaks charge, DRAM requires control circuitry to “refresh” the stored data by reading each cell's stored value and writing it back. This refresh operation occurs as often as every few milliseconds. DRAM can structurally achieve a higher memory density than SRAM; therefore, it is cheaper and has broader applications in volatile memory.
In addition, there is a non-volatile memory commonly referred to as Flash. Flash memory devices are generally classified into NAND flash memory devices and NOR flash memory devices. While NOR flash memory devices include memory cells that are independently connected to bit lines and word lines and have an excellent random access time, NAND flash memory devices include memory cells that are connected in series so that only one contact per cell string is necessary. Therefore, NAND flash memory devices have an excellent degree of integration. Accordingly, NAND structures are mainly used in high-integrated flash memory devices.
A well-known NAND flash memory device includes a memory cell array, a row decoder and a page buffer. The memory cell array includes word lines elongating along rows, bit lines elongating along columns, and cell strings corresponding to the respective bit lines.
FIG. 4 presents the prior art 1T1C DRAM cell, which is the current industry standard due to its simplicity and small size. Successive DRAM generations have gradually reduced the cell size by shrinking both the transistor and capacitor, thereby achieving higher memory densities and lower production costs. However, since the 1 Mb DRAM generation in the mid-1980's, the capacitor has been forced to assume increasingly complicated 3-dimensional structures to store enough charge for a given cell size. While variations on the standard DRAM design have replaced the capacitor with an alternate secondary storage unit such as a resistor, magnetic tunnel junction (MTJ), etc., the presence of a secondary component has limited DRAM's continued scalability.
While early MOS memory was originally a stand-alone component within the computer, recent memory development has focused on the integration of memory and logic on a single chip—a feat that allows for improved performance, lower power consumption, less board space requirements, and reduced number of chips, among other advantages. FIG. 2 illustrates the basic layout of embedded memory in a System-on-a-Chip (SoC). While SRAM is widely used as an embedded memory, it is subject to standby power dissipation and increased susceptibility to soft errors. Embedded DRAM can bypass these challenges and also allow for higher memory densities; however, the presence of the capacitor in existing DRAM designs has made it incompatible with standard CMOS processes.